//--------------------------------------------------------------------------------------------
//    : 
//      Component name  : fpround
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPround(SIG_in, EXP_in, SIG_out, EXP_out);
   parameter              SIG_width = 28;
   input [SIG_width-1:0]  SIG_in;
   input [7:0]            EXP_in;
   output [SIG_width-1:0] SIG_out;
   reg [SIG_width-1:0]    SIG_out;
   output [7:0]           EXP_out;
   
   assign EXP_out = EXP_in;
   
   
   always @(SIG_in)
      if (SIG_in[2] == 1'b0)
         SIG_out <= SIG_in;
      else
         SIG_out <= {(SIG_in[SIG_width - 1:3] + 1), 3'b000};
   
endmodule
